Presenting Friday, January 25th, at 2PM EST
Task 3.6: Cognitive Architectures
In-memory computing has
emerged as a promising solution to address the logic-memory performance gap. We
propose design techniques using monolithic-3D integration to achieve reliable multi-row
activation which in turn help in computation as part of data readout. Our
design is 1.8x faster than the existing techniques for Boolean computations. We
quantitatively show no impact to cell stability when multiple rows are
activated and thereby requiring no extra hardware for maintaining the cell
stability during computations. In-memory digital to analog conversion technique
is proposed using a 3D-CAM primitive. The design utilizes relatively low
strength layer-2 transistors effectively and provides 7x power savings when
compared with a specialized converter in-memory. Lastly, we present a linear
classifier system by making use the above-mentioned techniques which is 47x
faster while computing vector matrix multiplication using a dedicated hardware
engine.
