(Siddhartha Balakrishna Rai is presenting on Wed. 3/25/20)
This talk is a design space exploration of the hardware (where? how many? how to interface?) and software (how to place data? how to map computations?) choices for placing RISCV cores within the rank, chip, and bank of the DIMM slots in the DRAM hierarchy to take advantage of the locality vs. parallelism trade-offs for speeding up Map-Reduce workloads.
